Technical Specifications

Host Bus Interface:
PCI Rev. 2.1 Electrical Interface.
PCI full size board form factor.
Memory Mapped Interface.

Network Interfaces:
8 Software configurable T1s or E1s (ANSI T1.408, ITU-T G.703)
75 Ohm or 100/120 Ohm line termination

H.100 Interface:
32 x 2, 4, or 8 Mbit/s highways
256 channels switchable externally
1024 channels switchable locally
Backward compatible with MVIP H.100 Interface:

DSP Resources (with Optional ASM Daughter Boards):
Vidar-55x4-ASM: 4x TI TMS320VC5510 DSPs (400 MIPS each).
Vidar-5x4-ASM: 4 x TI TMS320C548/549 DSPs (80 MIPS each).

HDLC Resources:
Support for 3 HDLC channel/access standard.
Vidar-55x4-ASM: Optional 96 HDLC channels with support for super- and sub-channels.
Vidar-5x4-ASM: Optional 24 HDLC duplex channels with support for super- and sub-channels.

DSP Programming Interface:
SW development in ANSI C and C++
Open interface with standard 3rd party tools

DSP Applications:
DTMF generation and detection
MF generation and detection
FSK generation and detection
Speech compression, encoding and decoding

Switching Matrix:
2048x2048 Byte Time-Space Switch

T1/E1 Frame Formats:
Doubleframe
CRC Multiframe
4-Frame Multiframe
12-Frame Multiframe
Super Frame (SF)
Extended Super Frame (ESF)

T1/E1 Line Codes:
HDB3
B8ZS
AMI, AMI with ZCS

T1/E1 Signaling Types:
Channel Associated (e.g. Robbed bit)
Common Channel

Clocking sources:
On-board oscillator
Incoming T1/E1
H.100 bus external clock

Phone Features:
4 Analog Interfaces (Codecs) for handset connections