Technical Specifications

Host Bus Interface:
PCI Rev. 2.1 Electrical Interface.
PCI form factor.
Memory Mapped Interface.
SW configurable IRQ and Memory Window.

H.100 Interface:
32 x 8.196 Mbps highways

DSP Resources:
16 x TI TMS320C548
16 x 80 MIPS processing power

DSP Memory:
32 KWord internal on-chip (per DSP)
Up to 256KWord external (per DSP)

DSP Programming Interface:
SW development in ANSI C or assembly
Texas Instruments C compiler, assembler, linker
Code Composer debugger

Included DSP Applications:
DTMF generation and detection
MF generation and detection
FSK detection
HDLC Sending/Receiving
Raw Data Sending/Receiveing

Switching Matrix:
2048x2048 Byte Time-Space Switch

Clocking sources:
On-board oscillator
H.100 bus

Phone Features:
4 Analog Interfaces (Codecs) for handset / speaker connections